Computer Engineering

Neuromorphic Computing Architectures

Research on brain-inspired computing systems that mimic biological neural structures for efficient information processing and learning.

RESEARCH GAP FRONTIERS

Quantum Error Correction Codes

Development of fault-tolerant quantum computing methods through advanced error correction and syndrome measurement techniques.

RESEARCH GAP FRONTIERS

Edge AI Hardware Acceleration

Design of specialized processors and accelerators for deploying artificial intelligence models on resource-constrained edge devices.

RESEARCH GAP FRONTIERS

Photonic Integrated Circuit Design

Creation of optical computing systems using photonic components for high-speed data processing and communication.

RESEARCH GAP FRONTIERS

Post-Quantum Cryptographic Hardware

Engineering cryptographic accelerators resistant to quantum computing attacks using lattice-based and other quantum-safe algorithms.

RESEARCH GAP FRONTIERS

In-Memory Computing Architectures

Development of processors that perform computation directly within memory structures to reduce data movement overhead.

RESEARCH GAP FRONTIERS

Reconfigurable Computing Platforms

Research on field-programmable gate arrays and dynamic reconfigurable hardware for adaptable computational systems.

RESEARCH GAP FRONTIERS

Heterogeneous System Integration

Design methodologies for integrating diverse processor types and specialized accelerators into unified computing platforms.

RESEARCH GAP FRONTIERS

Cache Coherence Optimization

Investigation of advanced cache protocols and memory consistency models for multi-core and many-core processors.

Machine Learning Hardware Accelerators

Design of specialized silicon for efficient training and inference of deep neural networks at scale.

3D Chip Stacking Technology

Research on three-dimensional integrated circuit packaging with through-silicon vias for improved performance and density.

Power-Efficient Processor Design

Development of ultra-low-power computing architectures through voltage scaling, clock gating, and power management techniques.

Network-on-Chip Architectures

Design of scalable on-chip interconnect networks for many-core processors using routing and switching innovations.

Security Hardware Verification

Formal verification and testing methods for ensuring cryptographic hardware implementations resist side-channel attacks.

GPU Compiler Optimization

Development of compiler techniques for maximizing performance and efficiency of graphics processor code generation.

Approximate Computing Systems

Engineering hardware that trades precision for power efficiency through controlled approximation in computation.

Real-Time System Scheduling

Research on predictable scheduling algorithms and hardware mechanisms for deterministic real-time computing applications.

Analog Computing Circuits

Design of analog and mixed-signal processors for specialized computation in AI, signal processing, and sensing.

Hardware Security Primitives

Development of secure hardware components including true random number generators and tamper-resistant modules.

Embedded Systems Design Automation

Tools and methodologies for automated hardware-software co-design and synthesis of embedded computing systems.

Thermal Management in Processors

Research on cooling technologies, thermal aware scheduling, and packaging for managing heat in high-performance chips.

Wireless Communication Hardware

Design of RF transceivers and baseband processors for modern wireless standards and software-defined radio platforms.

Internet of Things Microcontrollers

Development of ultra-low-power microcontroller architectures optimized for IoT sensor networks and edge computing.

Biological Signal Processing Hardware

Specialized processors for real-time biomedical signal acquisition, processing, and analysis in wearable devices.

Computer Vision Processors

Engineering dedicated hardware accelerators for image processing and computer vision algorithms in autonomous systems.

Data Center Network Architecture

Research on scalable interconnect designs, switching fabrics, and networking hardware for cloud computing infrastructure.

Fault Tolerance in Distributed Systems

Hardware and architectural mechanisms for achieving reliability and availability in large-scale distributed computing systems.

Autonomous Vehicle Computing Hardware

Design of safety-critical, real-time processing systems for sensor fusion and decision-making in autonomous vehicles.

Quantum Computing Gate Implementation

Physical realization of quantum logic gates using superconducting qubits, trapped ions, or photonic platforms.

Memory Interface Optimization

Research on high-bandwidth memory controllers, interconnects, and protocols for improved system memory performance.

Specialized AI Processor Design

Development of domain-specific architectures for particular AI tasks including natural language processing and computer vision.

Side-Channel Attack Mitigation

Hardware countermeasures against timing, power, and electromagnetic side-channel attacks in cryptographic systems.

Testability and Built-in Self-Test

Design-for-test methodologies and on-chip self-testing mechanisms for ensuring chip quality and reliability.

Software-Defined Hardware

Research on dynamically reconfigurable hardware controlled by software for flexible computational resource allocation.

Biosignal Interface Electronics

Development of analog front-end circuits for acquiring and conditioning biomedical signals in implantable devices.

Blockchain Hardware Acceleration

Design of cryptographic accelerators for blockchain consensus mechanisms and smart contract execution.

System-on-Chip Integration

Research on integrating multiple functional blocks including processors, memory, and peripherals on single chips.

Processor Microarchitecture Innovation

Development of novel instruction execution models, pipeline designs, and branch prediction strategies for performance.

5G and Beyond Mobile Hardware

Design of baseband and RF hardware for next-generation wireless standards with extreme bandwidth and low latency.

Chip Reliability and Degradation

Research on predicting and mitigating device aging, electromigration, and parametric failures in integrated circuits.

Virtual Reality Rendering Hardware

Specialized graphics and processing hardware for high frame rate, low latency VR applications.

Spintronics Computing Devices

Development of magnetic-based computing elements using electron spin for energy-efficient information processing.

FPGA Synthesis Algorithms

Design automation tools for optimizing FPGA placement, routing, and timing of user-defined logic circuits.

Multicore Processor Synchronization

Research on synchronization primitives, locks, and memory barriers for efficient concurrent programming on multicore systems.

Gesture Recognition Hardware

Specialized accelerators for real-time human gesture and motion recognition from sensor inputs.

Supply Chain Security in Semiconductors

Research on detecting and preventing hardware trojans and malicious modifications in semiconductor manufacturing.

Mixed-Signal Circuit Design

Development of integrated circuits combining analog and digital components for sensing and signal conversion.

Cyber-Physical System Hardware

Design of embedded processors and interfaces for real-time control of physical systems in industrial applications.

High-Performance Computing Interconnects

Research on scalable, low-latency network fabrics for connecting thousands of processors in supercomputing systems.

Optical Network-on-Chip Design

Research on integrating optical communication channels within chip architectures to overcome electrical interconnect bandwidth limitations and reduce latency in multicore systems.

Quantum-Classical Hybrid Processor Architecture

Development of processor designs that seamlessly integrate quantum processing units with classical computing elements for practical quantum advantage applications.

Neuromorphic Vision Sensor Integration

Research on event-driven visual sensors that mimic biological vision systems and their integration with neuromorphic processing hardware for real-time applications.

Silicon Photonics for Computing

Investigation of silicon-based photonic components for high-speed data processing and signal routing to replace traditional electronic interconnects in computing systems.

Approximate Arithmetic Unit Design

Design of specialized arithmetic circuits that trade computational precision for significant power savings in applications tolerating bounded errors.

Reconfigurable In-Memory Processing Units

Development of computing architectures that perform data processing directly within memory arrays to minimize data movement and improve energy efficiency.

Hardware-Based Machine Learning Security

Research on hardware accelerators designed specifically to protect machine learning models from adversarial attacks and model extraction threats.

Programmable Logic Verification Methods

Advanced formal verification techniques and methodologies for ensuring correctness of complex programmable logic and reconfigurable hardware designs.

Thermal-Aware Circuit Synthesis

Automated synthesis techniques that incorporate thermal constraints and hotspot predictions during the design of high-performance computing circuits.

Emerging Memory Technology Integration

Hardware design research for integrating novel memory technologies including memristors, phase-change memory, and ferroelectric RAM into processor hierarchies.

Quantum Dot Transistor Engineering

Research on designing and manufacturing quantum dot-based transistors as potential successors to traditional silicon CMOS technology at nanoscale dimensions.

Network Slicing Hardware Implementation

Development of hardware architectures that enable virtualized network slices with guaranteed performance isolation and resource allocation guarantees.

Secure Enclave Architecture Design

Research on trusted execution environment hardware designs that provide isolated computation spaces resistant to both software and physical attacks.

Radiation-Hardened Circuit Design

Design techniques for creating computing circuits robust against ionizing radiation effects for aerospace and high-energy physics applications.

Heterogeneous Memory Hierarchy Optimization

Research on managing multiple diverse memory technologies with different latency, bandwidth, and power characteristics within unified computing systems.

Soft Error Resilience at Sub-5nm

Investigation of soft error mechanisms at advanced nodes and development of mitigation techniques for reliability in cutting-edge semiconductor processes.

Time-Sensitive Networking Hardware Support

Hardware design for real-time network packet processing with deterministic latency and jitter requirements for industrial and critical infrastructure systems.

Tensor Processing Architecture Innovation

Development of specialized processor designs optimized for tensor operations and multi-dimensional data manipulation in artificial intelligence workloads.

Delay-Oriented Circuit Characterization

Methodologies for accurate delay prediction and characterization of circuits under variable process corners, voltage, and temperature conditions.

Hardware-Software Co-Design Frameworks

Development of integrated design methodologies and tools for optimizing the partition and interaction between hardware and software components.

Cryogenic Computing Processor Design

Research on processor architectures optimized for operation at cryogenic temperatures for quantum computing control and signal processing.

Configurable Data-Flow Accelerators

Design of dynamically reconfigurable hardware accelerators that adapt their computational patterns to match variable workload characteristics.

Supply Chain Hardware Integrity Verification

Techniques for verifying authenticity and integrity of semiconductor components throughout manufacturing, distribution, and deployment pipelines.

Mixed-Precision Arithmetic Acceleration

Hardware design for efficiently supporting simultaneous operations at multiple floating-point and fixed-point precision levels with minimal performance overhead.

Aging-Aware Performance Prediction

Development of models and hardware mechanisms to predict and compensate for performance degradation caused by device aging over system lifetime.

Standardized On-Chip Bus Protocols

Research on designing and standardizing scalable interconnect protocols for efficient communication between diverse intellectual property blocks on chips.

Transactional Memory Hardware Implementation

Hardware support for transactional memory semantics enabling simplified parallel programming with conflict detection and automatic conflict resolution.

Molecular-Scale Computing Devices

Investigation of molecular computing elements and their assembly into functional circuits as a post-silicon computing paradigm.

Intermittent Computing Hardware Design

Hardware architectures for energy-harvesting systems that operate with frequent power interruptions while maintaining computational progress and state consistency.

Synchronization Primitive Hardware Acceleration

Design of specialized hardware for efficient implementation of synchronization mechanisms like barriers, locks, and atomic operations in parallel systems.

Heterogeneous Process Technology Integration

Research on combining multiple semiconductor process nodes and technologies within single chips to optimize area, power, and performance.

Graph Processing Hardware Acceleration

Development of specialized processor designs for accelerating graph algorithms and irregular memory access patterns in graph analytics applications.

Energy Harvesting Interface Circuits

Design of ultra-low-power interface circuits for converting diverse ambient energy sources into usable electrical power for embedded systems.

In-Situ Performance Monitoring Hardware

Development of embedded monitoring hardware for real-time observation of power, temperature, and performance metrics within executing processors.

Electrochemical Computing Substrates

Research on computing systems based on electrochemical processes and ion transport as alternative computing substrates to traditional electronics.

Custom Instruction Set Acceleration

Design methodologies for creating application-specific instruction sets and hardware support to achieve optimal performance for specialized workloads.

Probabilistic Computing Circuits

Hardware design exploiting probabilistic computation techniques to reduce power consumption and computational complexity in signal processing and inference.

Multi-Wavelength Optical Computing

Research on computing systems using multiple optical wavelengths for data encoding and manipulation to increase information density and processing capacity.

Dynamic Voltage and Frequency Scaling

Hardware mechanisms and control algorithms for real-time adjustment of processor voltage and frequency to optimize power-performance tradeoffs.

Fault Injection Testing Methodologies

Advanced techniques for injecting faults into hardware designs to evaluate system resilience and validate fault tolerance mechanisms.

Biosensor Interface Conditioning Circuits

Design of analog front-end circuits for amplifying, filtering, and digitizing weak biosensor signals with minimal noise and power consumption.

Massively Parallel Memory Interface Design

Development of memory interfaces supporting thousands of parallel data streams with predictable latency for high-throughput computing applications.

Hardware Trojan Detection and Prevention

Research on identifying and preventing malicious modifications integrated into hardware designs during manufacturing or design compromise.

Reversible and Adiabatic Computing

Investigation of computing paradigms based on reversible logic and adiabatic charge transfer to approach theoretical limits of energy efficiency.

Specialized Signal Processing Processors

Design of hardware architectures optimized for digital signal processing operations including filtering, transforms, and statistical computations.

Stochastic Computing Hardware

Development of processors using stochastic bit-streams and probabilistic computing principles to achieve extreme energy efficiency for approximate applications.

Augmented Reality Display Hardware

Research on specialized display processors and optical components for creating lightweight, low-power augmented reality displays.

Near-Field Communication Hardware

Design of integrated circuits for short-range wireless communication with focus on power efficiency and interference resilience.

Analog Neural Network Acceleration

Development of analog-domain hardware implementing neural network computations directly in continuous-time circuits for extreme efficiency.

Deterministic Network Switching Fabric

Hardware design for network switches with guaranteed bounded latency and zero packet loss for real-time communication requirements.

Cryogenic CMOS Circuit Design

Research on designing complementary metal-oxide-semiconductor circuits operating at liquid nitrogen temperatures for quantum computing interfaces and scalable qubit control.

Neuromorphic Sensorimotor System Integration

Development of hardware systems that integrate brain-inspired sensors and actuators for autonomous robotics and adaptive control applications.

Memristor-Based Neural Network Hardware

Development of analog neural computing systems using memristive crossbar arrays for energy-efficient deep learning inference.

Chiplet-Based Heterogeneous Integration

Research on designing modular chiplet architectures with advanced interconnects for scalable and flexible multi-die systems.

Time-to-Digital Converter Optimization

Study of high-resolution time measurement circuits for LiDAR, ranging, and precision timing applications in autonomous systems.

Approximate Arithmetic Logic Units

Design of specialized computational units that trade accuracy for power efficiency in error-tolerant applications.

Accelerated Graph Processing Hardware

Development of specialized processors for graph neural networks and graph database operations in machine learning workloads.

Heterogeneous Memory Hierarchy Design

Research on multi-tier memory systems combining SRAM, DRAM, NVM, and emerging technologies for optimal performance per watt.

Domain-Specific Quantum Processors

Development of specialized quantum processing units tailored for optimization, simulation, and machine learning applications.

Soft Error Resilience Architecture

Design of hardware mechanisms for detecting and correcting radiation-induced single-event upsets in advanced technology nodes.

Reconfigurable Dataflow Architectures

Study of hardware platforms that dynamically reconfigure computation patterns for diverse algorithmic workloads.

Trusted Hardware Root of Trust

Research on secure processor elements that establish cryptographic trust foundations for system-wide security.

Spiking Neural Network Accelerators

Development of specialized hardware for temporal spike-based neural computations with ultra-low power consumption.

Terahertz Integrated Circuit Design

Development of integrated circuits operating in terahertz frequency bands for imaging and communication applications.

Machine Learning Model Compression Hardware

Research on hardware architectures supporting neural network quantization, pruning, and knowledge distillation operations.

Nanowire Transistor Fabrication

Study of device-level engineering for gate-all-around nanowire transistors enabling continued Moore''s law progression.

Stochastic Computing Circuits

Research on probabilistic computation methods using stochastic bit streams for fault-tolerant and power-efficient processing.

Coherence Protocol Innovation

Design of advanced cache coherence protocols for many-core processors reducing bandwidth and latency overhead.

Heterogeneous Task Scheduling Algorithms

Development of runtime scheduling policies for distributing workloads across diverse processor types and accelerators.

Silicon Interposer Technology

Research on high-density interconnect layers for enabling chiplet integration with minimal latency and power loss.

Transient Fault Detection Mechanisms

Study of lightweight hardware techniques for identifying and recovering from temporary processing errors.

Analog-In-Memory Computing

Development of analog compute-in-memory systems performing matrix operations within memory arrays for neural networks.

Crossbar Array Optimization

Research on improving switching density and control circuitry in two-dimensional resistive memory arrays.

Quantum Annealing Hardware Implementation

Development of physical systems implementing quantum annealing for optimization problem solving applications.

Lightweight Cryptography Hardware

Design of minimal-resource cryptographic engines for resource-constrained IoT and embedded devices.

Neuromorphic Vision Sensor Design

Research on event-driven vision sensors that emit spikes asynchronously for low-latency visual processing.

Non-Volatile Memory Controller Design

Study of hardware controllers managing NAND flash, phase-change memory, and emerging non-volatile technologies.

Ultra-Low Power Wake-up Detection

Development of specialized circuits consuming minimal power while monitoring for activation events in sleeping systems.

Tensor Processing Unit Architectures

Design of hardware specifically optimized for multi-dimensional tensor operations in machine learning inference.

Photoacoustic Imaging Signal Processing

Research on hardware accelerators for real-time signal processing in photoacoustic medical imaging systems.

Clock Distribution Network Design

Study of low-skew, low-power clock generation and distribution architectures for large-scale processors.

Molecular Computing Interface Hardware

Development of electronic interfaces between silicon processors and molecular computing or DNA computing systems.

Resonant Tunneling Diode Circuits

Research on negative differential resistance devices for compact high-speed switching and oscillation applications.

Flexible Electronics Integration

Study of processor and sensor designs on flexible substrates for wearable and biomedical applications.

Interconnect Repeatability Analysis

Research on metal line performance variation in advanced nodes and mitigation techniques for signal integrity.

Sparse Tensor Accelerator Design

Development of specialized hardware efficiently processing sparse data matrices in scientific computing applications.

Ferroelectric Field-Effect Transistors

Study of ferroelectric gate materials for low-power memory and logic integration in next-generation devices.

Real-Time Video Codec Hardware

Design of specialized processors implementing H.265, AV1, and emerging codecs for streaming and surveillance.

Probabilistic Error Correction Codes

Research on hardware implementations of belief propagation and iterative decoding for advanced error correction.

Programmable Logic Array Synthesis

Study of automated design tools for mapping complex functions onto programmable logic array structures.

Graphene Nanoribbon Transistors

Development of carbon-based transistors for ultra-high-frequency and low-power computing applications.

Approximate Neural Network Inference

Research on hardware supporting lossy neural network computation for enhanced efficiency with graceful accuracy degradation.

Spin-Orbit Torque Memory Device

Study of magnetic memory elements using spin-orbit interactions for ultra-fast non-volatile storage.

RISC-V Custom Instruction Extensions

Development of application-specific instruction set extensions on open RISC-V architecture for domain specialization.

Optical Signal Integrity Analysis

Research on characterizing and mitigating dispersion, nonlinearity, and noise in silicon photonic links.

Tensor Memory Architecture

Design of specialized memory hierarchies with native support for multi-dimensional tensor access patterns.

Entropy Source Integration

Study of on-chip true random number generators and entropy accumulation for cryptographic applications.

Neuromorphic Sensor Interface Design

Development of hardware interfaces that directly process event-driven neuromorphic sensor data for real-time perception applications.

Silicon Photonics Modulator Optimization

Optimization of silicon-based optical modulators for high-speed intra-chip and inter-chip communication with minimal power consumption.

Quantum-Classical Hybrid Accelerator Codesign

Investigation of hardware architectures that seamlessly integrate quantum processing units with classical computing resources for hybrid algorithms.

Reliability-Aware Circuit Design Techniques

Methods for designing circuits that maintain functional integrity under process variations, aging, and environmental stress conditions.

Extreme-Scale Memory Architecture

Research on novel memory hierarchies and technologies for managing exabyte-scale data in next-generation computing systems.

Reconfigurable Accelerator Fabric Design

Development of dynamically reconfigurable hardware fabrics that adapt to varying computational workloads and algorithms.

Advanced Packaging and Interconnect Technology

Investigation of chiplet packaging techniques, advanced substrates, and 3D interconnects for ultra-dense system integration.

Transient Computing Systems Design

Architecture and implementation of computing systems that harvest ambient energy and operate transiently without batteries.

Hardware-Software Codesign for Streaming

Joint optimization of hardware and software for real-time processing of continuous high-bandwidth data streams.

Approximate Neural Network Hardware

Hardware accelerators exploiting neural network error tolerance for ultra-low power approximate computing implementations.

Millimeter-Wave Communication Transceiver

Design of highly integrated mmWave transceiver circuits and beamforming arrays for next-generation wireless systems.

Time-Series Acceleration Hardware

Specialized processor architectures for accelerating time-series analysis and forecasting in edge computing environments.

Robotic Control System Hardware

Embedded computing platforms for real-time robot control with deterministic latency and high computational efficiency.

Secure Hardware Enclave Architecture

Design of isolated hardware execution environments protecting sensitive computations against side-channel and physical attacks.

Analog Neuromorphic Learning Circuits

Analog and mixed-signal circuits implementing on-chip learning mechanisms inspired by biological neural systems.

Real-Time Computer Vision Processor

Specialized hardware architectures for real-time processing of video streams with efficient object detection and tracking.

Modular Reconfigurable System Design

Research on modular computing platforms that dynamically reconfigure hardware components based on application requirements.

Spiking Neural Network Hardware

Custom hardware implementations of spiking neural networks with event-driven computation for ultra-low power AI.

Radiation-Hardened Computing Systems

Design techniques for computing systems resistant to radiation-induced errors in aerospace and space applications.

Distributed Ledger Hardware Acceleration

Specialized hardware accelerators for consensus algorithms and cryptographic operations in distributed ledger systems.

Network Function Virtualization Hardware

Hardware acceleration platforms for network service chains and software-defined networking packet processing.

Lightweight Cryptography Processor Design

Efficient hardware implementations of resource-constrained cryptographic algorithms for IoT and edge devices.

Edge Machine Learning Inference Engine

Compact hardware accelerators for running pre-trained deep learning models on resource-limited edge devices.

Fault-Tolerant System Architecture

Computing architectures incorporating redundancy and error detection mechanisms for mission-critical applications.

Scalable Network Router Architecture

High-throughput router design with advanced packet scheduling and switch fabric architectures for data centers.

Biological Signal Sensor Interface

Ultra-low-noise analog front-end circuits for biomedical signal acquisition and preprocessing on-chip.

Tensor Processing Unit Architecture

Custom hardware architectures optimized for tensor operations in machine learning and scientific computing.

Intermittent Computing Power Management

Hardware and firmware techniques for managing computation across intermittent power availability in energy-harvesting systems.

Real-Time Stream Processing Hardware

Specialized processors for continuous stream analytics with bounded latency guarantees in data acquisition systems.

Full-Duplex Wireless Transceiver Circuit

Integrated circuitry enabling simultaneous transmission and reception on the same frequency channel with self-interference cancellation.

DNA Storage Interface Electronics

Control electronics and signal processing circuits for interfacing with DNA-based storage systems.

Cross-Layer Optimization Framework

Methodology for joint optimization across circuit, architecture, and system layers to achieve performance and efficiency goals.

Drone Control System Architecture

Embedded computing platforms for autonomous flight control with sensor fusion and real-time decision-making capabilities.

Satellite Communication Payload Hardware

Compact and radiation-tolerant hardware for satellite communication processing and signal conditioning.

Smart Grid Gateway Architecture

Computing platform for distributed energy resource management and grid communication in smart electrical systems.

Medical Implant Biocompatible Electronics

Miniaturized biocompatible processing and communication circuits for implantable medical device systems.

Graph Processing Accelerator Design

Hardware architectures optimized for irregular memory access patterns in graph algorithm processing.

Virtual Memory Management Hardware

Advanced translation lookaside buffer and page table walker designs for efficient virtual address translation.

Chiplet-Based Modular Architecture Design

Research focuses on designing and integrating multiple specialized chiplets through advanced interconnect technologies to achieve scalable and cost-effective heterogeneous computing systems.

Tensor Processing Unit Optimization

Investigation of specialized hardware architectures for accelerating tensor computations in deep learning, focusing on dataflow optimization and memory bandwidth efficiency.

Collaborative Multi-Agent Computing

Hardware platforms enabling coordinated computation across multiple autonomous agents with minimal communication overhead.

Optical Switching Fabric Control

Control and management hardware for optical circuit switches in reconfigurable data center networks.

Transient Computing and Energy Harvesting

Research on designing processors that operate intermittently using harvested environmental energy with intelligent checkpointing and state management techniques.

Haptic Feedback Interface Hardware

Actuator driver circuits and control systems for haptic rendering in immersive user interfaces.

Silicon Photonics Interconnect Systems

Study of integrated optical communication pathways within silicon chips to overcome electrical interconnect bottlenecks in high-performance computing architectures.

Distributed Machine Learning Edge Device

Hardware platform enabling federated learning and collaborative training across edge computing nodes.

Time-Sensitive Networking Hardware

Real-time network interface cards and switches supporting deterministic packet delivery for industrial automation.

Graph Processing Hardware Accelerators

Design of specialized computing units optimized for graph neural networks and irregular data patterns with efficient memory access patterns and communication.

Backscatter Communication Circuits

Research on ultra-low-power wireless communication hardware that modulates ambient signals for battery-free IoT devices and sensor networks.

Holographic Display Driver System

High-speed modulation electronics for spatial light modulators in holographic display systems.

Neuromorphic Event-Based Vision Sensors

Development of bio-inspired visual sensors that asynchronously capture pixel-level changes, enabling low-latency and energy-efficient computer vision applications.

Memristor-Based Computing Systems

Investigation of memristive devices as fundamental computing and storage elements for creating ultra-dense, low-power neuromorphic and analog computing platforms.

Neuromorphic Event-Driven Processing Systems

Research on designing ultra-low-power computing architectures that process asynchronous event-based data streams inspired by biological neural systems, with applications in real-time sensory processing and autonomous robotics.

Quantum-Classical Hybrid Processor Design

Research on seamlessly integrating quantum processing units with classical processors to efficiently execute hybrid algorithms and manage quantum-classical data exchange.